The invention relates generally to Metal-Oxide-Silicon (MOS) Read-Only Memories (ROMs) and more particularly to nonvolatile MOS charge coupled memory devices.
There are two basic classes of solid state read only memories (hereinafter referred to as ROMs)-namely, random access memories and serial access memories. Random access MOS ROMs are generally well known. They typically consist of a matrix of Metal-Oxide-Silicon-Field-Effect Transistors (MOSFETs) that have been constructed with an alterable threshold voltage which is used to electrically indicate the storage of a binary "1" or "0". The second class of ROMs, i.e., serial access memories are not known to be presently commercially available as MOS devices.
A typical solid-state random access ROM is a MNOS (Metal Nitride Oxide Semiconductor) memory device such as described by Dov Frohman and Bentchowsky in Proceedings IEEE, Vol 58, August 1970 pages 1207-1219. The MNOS structure described in this publication is configured in the form of a field-effect transistor fabricated on a semiconductor substrate having an insulated gate electrode and source and drain terminals that "current access" the stored charge in the transistor. A composite insulating layer disposed between the gate electrode and the semiconductor substrate of the transistor consists of a thin layer of silicon oxide on which a layer of silicon nitride has been applied. By applying a voltage pulse on the gate electrode, charge carriers are transported from the semiconductor substrate to the thin silicon oxide layer by means of a phenomenon known as tunnelling. The number of charge carriers trapped at the interface of the silicon oxide layer and the silicon nitride layer determines the threshold voltage of the transistor, which voltage in turn controls the magnitude of the current flow between the source and drain terminals for a specified read voltage on the gate electrode. However, the problem encountered with this prior MNOS structure is that it requires at least one transistor per bit of binary information, so that the packing density is very small and limited.
Another method of determining the threshold voltage of a field-effect transistor gate in the above type of MNOS structure is by injection of charge created during an avalanche breakdown in the semiconductor substrate of tee transistor. A semiconductor memory device using this principle is known in the art as a FAMOS (Floating-Gate Avalanche Metal Oxide Semiconductor) structure, and one such structure of this type is described by Dov Frohman and Bentchowsky in IEEE Journal of Solid-State Circuits, Vol. SC6, October, 1971, pages 301-306. The device described in the latter publication is a field-effect transistor with a source, a drain, and an insulated floating gate electrode in the form of a nonconnected conductive layer which is usually surrounded by insulating material and disposed above the surface of the semiconductor substrate. By applying a reverse bias of sufficient magnitude across the source substrate PN junction or the drain-substrate PN junction to produce avalanche breakdown, charge carriers are generated at the junction. On account of the electrical field applied across the PN junction at reverse breakdown, the energy of these charge carriers reaches a high level such that these carriers are capable of travelling from their energy band in the semiconductive substrate to a corresponding energy band in the insulating layer below the gate electrode. Such charges travelling in the insulating layer near the floating gate electrode will therefore charge this electrode. Thus, during operation of this FAMOS type device, electrons can move from the conduction band in the semiconductor substrate to the conduction band in the insulating layer. Conversely, holes of the valence band in the semiconductor substrate may shift to the valence band in the insulating layer. However, once again the important drawback of this latter avalanche injection structure is the inefficient packing density which results from the requirement of one transistor per bit to be stored in the structure.
An alernate method of cell operation frequently used in connection with a MNOS memory device of the above type is charge addressing the MNOS structure. This operation is accomplished by controlling the silicon oxide electric field strength and current density of the device which is dependent upon the magnitude of signal charge beneath a deep depleted MNOS capacitor formed by the device. In operation, the surface potential of this capacitor is collapsed and the silicon oxide electric field strength increases with an increase in silicon oxide tunnelling current. The transfer of signal charge from the device is typically accomplished using an output charge-coupled device (CCD). The combination of charge transfer and MNOS principles for signal control, address, and nonvolatile storage for this latter type of device has been set forth by K. Goser and K. Knaver in IEEE Journal of Solid-State Circuits, SC-9, pages 148-150, June 1974 and by Y. T. Chan et al in Applied Physics Letters, Vol. 22, pages 650-652, 15 June 1973. The charge storage sites of these MNOS structures are located inside a stepped dielectric 2-phase or 3-phase CCD shift register.
This latter MNOS device also has a poor packing density and an inadequate charge handling capability, both of which result in poor write characteristics and ineffective write/inhibit operation for the device. Additionally, high voltage clocks required for good transfer efficiency in these devices cause spurious write operation and poor read operation due to the large access time to the first stored bit, and these characteristics tend to degrade memory retention caused by small write and read disturbance effects.
A ROM CCD device that has a higher packing density than all of the above-identified prior art structures is a nonvolatile charge-addressed memory (NOVCAM) cell with parallel write and read-out injection for block-oriented random-access memory (BORAM) applications as set forth, for example, by White et al, in the IEEE Journal of Solid-State Circuits, Vol. SC10, No. 5, October 1975. The NOVCAM cell described in this publication comprises a combined CCD shift register and a thin-oxide MNOS memory structure to provide a higher packing density. However, the charge transfer efficiency of this latter device is severely degraded by the thin oxide at the MNOS surface, and therefore this circuit is not well suited for ROM CCD operation with high charge transfer efficiency.